The present invention relates generally to data caches, and more specifically to techniques for controlling, configuring, and testing such caches.
The use of a data cache is well known as a technique for overcoming some of the performance limitations that result from the mismatch between processor speed and main memory access time. This tends to be a problem with very fast CPU's. In brief, the technique entails providing a relatively small cache memory characterized by access times significantly less than that of the main memory. The contents of selected portions of main memory are copied into the cache memory, and memory accesses look to the cache to speed the data acquisition. In current high-end personal computers, the main memory is implemented as DRAM (dynamic RAM) chips, while the cache data RAM and tag RAM are implemented as SRAM (static RAM) chips which are much faster, but much more expensive for a given amount of memory.
A typical direct-mapped cache includes a cache data RAM containing cached data, and a tag RAM containing partial (high-order) address information. The cache is accessed by applying low-order address information as an index to the address inputs of the cache data RAM and the tag RAM, reading out the tag, and comparing the tag with the corresponding portion of the full address. If the two agree, the access is said to have resulted in a cache hit, and the contents of the cache data RAM for that address are supplied to the CPU. If the two do not agree, the memory access is said to have resulted in a cache miss, and the CPU must wait for the data to be brought in from the slower main memory.
As a specific example, a 64-kilobyte cache is addressable by a 16-bit address. An 8-bit tag, when combined with the 16-bit address, provides a 24-bit address which allows any memory location in a 16-megabyte memory to be cached. A 10-bit tag would allow caching of up to a 64-megabyte memory. In a typical configuration, the cache data RAM data ports are coupled to the local processor bus while the DRAM data ports are coupled to a buffered version of the local processor data bus. Buffers and separate control signals are needed to avoid both the DRAM and the cache trying to put data on the bus at the same time.
A typical cache memory will have valid bits associated with each entry. The valid bits indicate whether there is a valid entry in the cache. Invalid entries will be present, for example, when the system is started up before there have been any reads from the DRAM to put data into the cache. In addition, if the data in DRAM is modified, the corresponding cache entry for the previous data will become invalid.